https://tscircuit.com/techmannih/NEMA-34
https://tscircuit.com/techmannih/NEMA 34 Smart Motor Mounted Stepper Controller files
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https://tscircuit.com/techmannih/NEMA 34 Smart Motor Mounted Stepper Controller files
The post routing hook is up as three tscircuit PRs. The core PR is a draft until the props PR is merged and released. [props 939](https://github.com/tscircuit/props/pull/939) adds the pcbPostRoutingHook prop to <board and subcircuit <group , with the typed context the hook receiv
Hey, claude told me this: is it true for tscircuit? Also is there any way to edit small things in tscircuit without asking my claude / json to do it... I feel like would be faster for me to just manually adit small things. Thanks
For sure one of the reasons AI switches to "manual" routing is when the autorouter produces DRC errors. It is like "uhh that's impossible to resolve" so it stops trying to use the autorouter. We may be able to tell it about reroute autorouting phases as a workaround, not sure. Pr
what workflow do you guys recommend if autorouting doesnt do it for your board because its too complex? like export to kicad and back to tscircuit somehow or not sure whats the most seamless taking into account that i need jlcpcb compatible exports at the end of it
Proposal: Treat inferred trace length limits as warnings tscircuit automatically assigns a 1 mm maximum length to traces connected to detected decoupling capacitors. When placement exceeds this value, preflight currently stops autorouting for the entire board. This default should
mention what should we do about vias in crystal traces ?
woah the autorouting looks soo good.
mention these issues are blocking me from routing the AM62L board, a lot of progress was made, it's nearly there https://github.com/tscircuit/tscircuit autorouter/pull/2247 https://github.com/tscircuit/tscircuit autorouter/pull/2248 https://github.com/tscircuit/tscircuit autorout
I’m recreating the Adafruit Feather RP2040 USB Host board in TSCircuit from the official Eagle reference. Placement, netlist, TypeScript, and shorts checks pass. After adding the full support net connectivity, autorouting fails with: code sample PCB traces remain unrouted afterwa
can we have a new check called "tsci check silkscreen" to check the silkscreen overlaps with other courtyard , pad, other texts , .. etc ??
Hey folks. I am still rather new to tscircuit so if I am asking this in the wrong place lmk where I should ask. I have finished laying out a circuit in tscircuit and it seems to be working well for everything I need so far, except for traces. The autorouter seems to be creating s
BGA pads are now circles im concerned about autorouting and calculate packing and their approximation rects (also for pill pads)
Hey team! I tried to generate this pcb. Its a bit big, but it should be working and it takes 4h at the placement part. Is there a way to accelerate the autoplacement or all I need to do is buy a better CPU?
SEQUENTIAL TRACE AUTOROUTING IS BEING DISABLED! Major breaking change, but AI is just too shitty when it is allowed
very easy schematic trace solver fix
https://github.com/tscircuit/tscircuit autorouter/issues/1797 mention Could someone take a quick look and let me know whether I’m approaching this correctly and whether this behavior needs a fix?
placementDrcChecksDisabled doesn't seem to work when set on a <board . Even with placementDrcChecksDisabled={true}, autorouting is still skipped due to placement DRC errors, even though the error message tells users to set that prop to bypass the check. I traced it to what looks
While building a board in the tscircuit repo, I noticed something and wanted to check if it's intentional. I was trying to disable placement DRC so the autorouter could continue despite overlapping footprints. Circuit({ platform: { placementDrcChecksDisabled: true } }) works as e
mention https://github.com/tscircuit/tscircuit/actions/runs/29198090734/job/86664586201
I added some new stuff to the https://cad component viz.vercel.app/ check it out
Am I not getting something or is it a known limitation? https://tscircuit.com/editor?template=blank circuit board data:application/gzip;base64,H4sIAGodU2oAA7WSXUsrMRCG/0rIlYKN27V76hFXOBxBvBGt4o2RJW7HurI7WZJUKqX/3cl+tLWtWoTuzSYz77x5Mpkpz3AIE+HshJ/wrCi1cWwAKnXs2eiCSW78RnKJEmFSpVON1
my autorouting skipped 😭 , that is ok for me to have that DRC (e.g footprint overlap) .
mention
I'd like to train the AI in our skill to be able to resolve autorouter issues using <autoroutingphase / i think this would be much better than the AI constantly switching to sequential trace autorouting
Can someone look into this? https://github.com/tscircuit/tscircuit.com/issues/3704
mention
Something is most likely busted in the autorouter somehow and it's throwing more DRC errors and i had to add tsci build ignore errors to the smoke tests to unblock the pipeline. I don't think I caused this with jumper autorouting because jumper autorouting isn't being used on the