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astrimid - Maybe tscircuit is a wrong tool for ...

Maybe tscircuit is a wrong tool for a thing I'm building? Here's my use case: https://spice circuit simulation.vercel.app/ The schematic is nice to have really, circuit JSON and manual placement of critical probes and component states Is there someting similar to tscirciuit for v

Started by astrimidJul 12, 202632 messages

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astrimidoriginal post
Maybe tscircuit is a wrong tool for a thing I'm building? Here's my use case: https://spice-circuit-simulation.vercel.app/ The schematic is nice to have really, circuit JSON and manual placement of critical probes and component states Is there someting similar to tscirciuit for virtual benches like that?
astrimid
2 days in and I'm still fighting the tool and can't even run a simple simulation.
astrimid
My hope was I could use groups to show sections of schematic I'm interested in monitoring while simulating, or the whole circuit if not possible. But even placing 5 components in a row is someting schematic visualization is trying to loop in a circle and bend around. Displaying the whole circuit becomes a soup of net label flags.
Mustafa7
Use name on traces that will remove those long connection netlabels
astrimid
Even on schematic viewer examples, those netlabels appear to be auto generated. This is example12-spice-boost-converter.fixture.tsx
astrimid
any sane person would just connect M1 to the junction between L1 and D1, and that R1 resistor wouldn't be hanging alone in the corner
astrimid
is there any way to produce normal schematics layout, like in a textbook?
astrimid
with multiple loops
astrimid
right now it appears only a single loop is possible
Mustafa7
I am not sure if <@757706909351411845> would recommend using `schMaxTraceLength` coz currently the whole system of sch routing is based on a distance. However we would have to find a better solution for that
astrimid
is there any way to specify manual manhattan style routing?
Mustafa7
Yea schMaxTraceLength
Mustafa7
On board/group/subcircuit
astrimid
I mean, specify the exact line elbows using schX/schY
Mustafa7
No you cannot specify where the elbow should be
Seve
schMaxTraceLength could be used in this case to achieve more traditional long lines
Seve
I agree that this is poor routing and shouldnt have long labels in this case- it should just have lines.
Seve
<@1079361271687807026> i dont think distance is a good to use if its doing this kind of thing- the trace is better than the long labels
astrimid
I've set schMaxTraceLength high it seems to eliminate the strange net labels. But sometimes I want to disconnect explicitely. Is there a way to force the separate netlabel, e.g. multipe GND drains?
astrimid
``` <netlabel net="GND" connection=".V5_DC_IN .pin2" anchorSide="top" schX={3} schY={0.3} /> <netlabel net="GND" connection=".V_DC_IN .pin2" anchorSide="top" schX={3} schY={1.7} /> ``` Found a way, netlabels support schX/Y, although this doesn't eliminate the link between grounds
astrimid
small nitpick: netlabel anchorSide top/botom creates a ground symbol, while anchorSide left/right create a flag symbol. This is irrespective of the actual ground vs voltage source. I guess, the schematic/netlabels don't know the semantics behind the source/drain and negative and positive terminals?
Seve
Its based on the automatic or explicit net classification- you dont want the ground symbol
astrimid
Still confusing why some nets show up as ground symbol `V3_VC` is not a ground network, it's connected to pin1 of voltage source, how can it be GND?
Seve
Oh… i guess its just a bad choice- we use that for power but yea it should be different
Seve
Should be an arrow iirc
Seve
You’re looking for this right?
astrimid
arrow would be nice, yeah, but even a small circle would be ok. I'm not sure it tscircuit supports the ANSI/IEC and all the variations of symbols
astrimid
maybe some manual classification of netlabels? voltage source (circle), signal (flag) and sink (ground triangle/antenna)
Seve
We could support that explicitly- we maintain a large symbol library and can add that one
Seve
Idk if we would default to it, but we may be able to introduce a global setting
astrimid
stackexchange says the currently used symbol is ok. but only if it points up https://electronics.stackexchange.com/questions/298727/prefered-schematic-symbol-for-voltage-rail-and-bus-labels also, bus signals have directionality, didn't look into whether it's currently supported
Seve
Yea it would be simple to add a net label symbol override etc, i think its a good feature

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