shibo - @Seve we can try to auto compute the gr...

how does this API look?

<@757706909351411845> rename: https://github.com/tscircuit/props/pull/712

<@757706909351411845> https://github.com/tscircuit/core/pull/2523

<@757706909351411845> https://github.com/tscircuit/props/pull/713

btw, I gave a TI chip datasheet(it also had access to my 2 simulation circuits) to codex and told it to create a behavioral pspice model for it. using the generated pspice model I got the same results as the original model for the 2 simulations

hmm interesting- did it have access to the original?

The other thing is those PSPICE models are kind of widely available unencrypted, i wonder what we could do for models where there's a bit less data

some of the chips that don't have pspice available etc.

but good stuff

I told it to not look at the original model

you're right maybe they trained on those models

yea i mean it also probably looked haha

not exactly a clean environment

I'll try to do one that has no model available

it probably is almost automatically accidentally included

yea

https://github.com/tscircuit/props/pull/713

<@757706909351411845> rewrite: https://github.com/tscircuit/core/pull/2523

<@757706909351411845> https://github.com/tscircuit/docs/pull/770

<@757706909351411845> https://github.com/tscircuit/ti/pull/64

<@757706909351411845> i thought the changes were fixes not regressions, I fixed the regressions now: https://github.com/tscircuit/core/pull/2589

Can u include motivation in the pr description- i feel like i dont understand what/why we’re fixing this

I was trying to route one tight IC center-pad connection with a smaller trace width, but the autorouter kept outputting the default wider trace so the clearance issue stayed unchanged.

Ok this fix seems wrong tho? There’s a lot of core code

The fix would be in the autorouter OR just core needs to adjust the minTraceWidth etc?

I don’t understand this fix

Why would we pass trace widths on a per trace basis to fix the original issue- can you repro the original issue

the original issue was that using width on a single trace likes this: ``` <trace name="IC1_B2_SCL_CENTER_PAD" from="IC1.B2" to="net.SCL" width="0.06mm" /> ``` had no effect

I'll try to simplify the repro, and see if there is a more direct fix

Honestly sounds like an autorouter bug

<@757706909351411845> i believe it's not an autorouter issue because core was giving the autorouter the wrong input, I simplified the PR greatly, please review: https://github.com/tscircuit/core/pull/2589

ok tyty

<@757706909351411845> is it ok to say the global minTraceWidth is 0.15 when there are traces at 0.06?

it should be a computed from the smallest width we have, and if someone specifies the global minTraceWidth and there are traces smaller than that we error?

I think it's ok

i think `minTraceWidth` would better be named `defaultMinTraceWidth`

but it's ok

in general specificity overrides

idk it really depends on a couple things

i'm OK with your PR if it fixes things for now

but yea in general specificity (specific trace setting) overrides global settings

ultimately if this overcomplicates the autorouter code i'm down for something that doesn't make sense from an API perspective