# shibo - @Seve we can try to auto compute the gr... Channel: #contributor Source: https://discord.com/channels/1233487248129921135/1521182691628679188 Started: 2026-06-29T15:56:56.327000+00:00 Last activity: 2026-07-07T16:49:49.708000+00:00 ## shibo — 2026-06-29T15:56:55.892000+00:00 <@757706909351411845> we can try to auto compute the graph placements: https://github.com/tscircuit/props/pull/712 ## shibo — 2026-06-29T15:57:08.582000+00:00 how does this API look? ## shibo — 2026-06-29T17:04:42.351000+00:00 <@757706909351411845> rename: https://github.com/tscircuit/props/pull/712 ## shibo — 2026-06-29T17:55:57.356000+00:00 <@757706909351411845> https://github.com/tscircuit/core/pull/2523 ## shibo — 2026-06-29T21:06:45.449000+00:00 <@757706909351411845> https://github.com/tscircuit/props/pull/713 ## shibo — 2026-06-29T21:10:00.979000+00:00 btw, I gave a TI chip datasheet(it also had access to my 2 simulation circuits) to codex and told it to create a behavioral pspice model for it. using the generated pspice model I got the same results as the original model for the 2 simulations ## Seve — 2026-06-29T21:11:41.091000+00:00 hmm interesting- did it have access to the original? ## Seve — 2026-06-29T21:12:26.493000+00:00 The other thing is those PSPICE models are kind of widely available unencrypted, i wonder what we could do for models where there's a bit less data ## Seve — 2026-06-29T21:12:34.476000+00:00 some of the chips that don't have pspice available etc. ## Seve — 2026-06-29T21:12:36.435000+00:00 but good stuff ## shibo — 2026-06-29T21:12:37.816000+00:00 I told it to not look at the original model ## shibo — 2026-06-29T21:12:59.905000+00:00 you're right maybe they trained on those models ## Seve — 2026-06-29T21:13:07.559000+00:00 yea i mean it also probably looked haha ## Seve — 2026-06-29T21:13:13.459000+00:00 not exactly a clean environment ## shibo — 2026-06-29T21:13:29.171000+00:00 I'll try to do one that has no model available ## Seve — 2026-06-29T21:13:29.946000+00:00 it probably is almost automatically accidentally included ## Seve — 2026-06-29T21:13:32.490000+00:00 yea ## shibo — 2026-06-29T21:14:02.676000+00:00 https://github.com/tscircuit/props/pull/713 ## shibo — 2026-06-29T21:35:57.600000+00:00 <@757706909351411845> rewrite: https://github.com/tscircuit/core/pull/2523 ## shibo — 2026-06-30T17:38:16.892000+00:00 <@757706909351411845> https://github.com/tscircuit/docs/pull/770 ## shibo — 2026-07-06T16:50:50.204000+00:00 <@757706909351411845> https://github.com/tscircuit/ti/pull/64 ## shibo — 2026-07-07T13:48:53.105000+00:00 <@757706909351411845> i thought the changes were fixes not regressions, I fixed the regressions now: https://github.com/tscircuit/core/pull/2589 ## Seve — 2026-07-07T13:49:28.227000+00:00 Can u include motivation in the pr description- i feel like i dont understand what/why we’re fixing this ## shibo — 2026-07-07T13:53:03.614000+00:00 I was trying to route one tight IC center-pad connection with a smaller trace width, but the autorouter kept outputting the default wider trace so the clearance issue stayed unchanged. ## Seve — 2026-07-07T13:56:49.097000+00:00 Ok this fix seems wrong tho? There’s a lot of core code ## Seve — 2026-07-07T13:57:26.364000+00:00 The fix would be in the autorouter OR just core needs to adjust the minTraceWidth etc? ## Seve — 2026-07-07T13:57:33.661000+00:00 I don’t understand this fix ## Seve — 2026-07-07T13:58:55.565000+00:00 Why would we pass trace widths on a per trace basis to fix the original issue- can you repro the original issue ## shibo — 2026-07-07T14:01:48.918000+00:00 the original issue was that using width on a single trace likes this: ``` ``` had no effect ## shibo — 2026-07-07T14:02:28.059000+00:00 I'll try to simplify the repro, and see if there is a more direct fix ## Seve — 2026-07-07T14:49:54.092000+00:00 Honestly sounds like an autorouter bug ## shibo — 2026-07-07T16:09:46.844000+00:00 <@757706909351411845> i believe it's not an autorouter issue because core was giving the autorouter the wrong input, I simplified the PR greatly, please review: https://github.com/tscircuit/core/pull/2589 ## Seve — 2026-07-07T16:14:28.661000+00:00 ok tyty ## shibo — 2026-07-07T16:38:33.333000+00:00 <@757706909351411845> is it ok to say the global minTraceWidth is 0.15 when there are traces at 0.06? ## shibo — 2026-07-07T16:39:31.091000+00:00 it should be a computed from the smallest width we have, and if someone specifies the global minTraceWidth and there are traces smaller than that we error? ## Seve — 2026-07-07T16:46:51.908000+00:00 I think it's ok ## Seve — 2026-07-07T16:47:04.166000+00:00 i think `minTraceWidth` would better be named `defaultMinTraceWidth` ## Seve — 2026-07-07T16:47:10.071000+00:00 but it's ok ## Seve — 2026-07-07T16:47:15.566000+00:00 in general specificity overrides ## Seve — 2026-07-07T16:47:21.544000+00:00 idk it really depends on a couple things ## Seve — 2026-07-07T16:47:30.487000+00:00 i'm OK with your PR if it fixes things for now ## Seve — 2026-07-07T16:47:45.801000+00:00 but yea in general specificity (specific trace setting) overrides global settings ## Seve — 2026-07-07T16:49:49.708000+00:00 ultimately if this overcomplicates the autorouter code i'm down for something that doesn't make sense from an API perspective