Vivek Vijayan - Hi Guys.. Highlighted pins in t...

package url , if possible ?

Seems like a bug, provide us a repro. Somebody will take a look at this issue

I can take a look, just send a repro if possible

This issue seems occur when one <trace> element is used with more than two paths. Eg: <trace name="t_swdio" path={[".mcu .SWDIO", ".J_DEBUG .pin1", ".mcu.pin1"]} /> I will share a reproducible code later..

This usually happens to me when tscircuit decides GND net label is not worth rendering for some reason Try explicit <netlabel withc schX/Y for each pin.

is this `t_swc_ctrl_chg` also an bug i could help if it is; this is routed but still we can see the an label? <@809856037376491570>

<@1050759023194030111> did you put anything to force show the netlabel?

ig they are trace name

<trace from=.. to=.. name="t_sec_chg"/>

ig

ohh ok but we render trace name like labels?

yea

<@809856037376491570> <@757706909351411845> are lables ever put like this? to help with clutter prevention like in this case

<@1238122660345548882>

I think labels only make sense for traces that do not need to be routed. why put them for things that have their routes defined

and if we put may be a new style that will try to find a empty spot along the route and put the text their 🤷‍♂️

yea agree

<@1525187702029549659> would love if you have thoughts on this

The labels look very cluttered tbh

This could have been improved with `schPinSytle` to space the portLabels and increase the `schHeight`

Frankly, I don't understand terminology here. Are you talking about schematic traces? What does it mean "do not need to be routed"? what does it mean "have their routes defined"?

oh, you're not talking about pins without netlabels, are you?

you're talking about naming nets like this.

I think we can split this into two problems: 1. netlabel style: tscircuit doesn't really support all netlabel types only signal like flags, an only in one direction a) even for flags, when you set achnor side, it doesn't actually flip the label symbol (signal in vs signal out) b) gnd netlabel only renders in one style (if it renders) and sometimes leaves the pin stub out unconnected to any netlabel (when it wrongly thinks the port already has proper symbol displayed on schematics) 3) third type of netlabel when it is just a text annotation over the wire/trace, not a flag or power/gnd ref. To recap, there are 3 types of electrical signals than need special symbols (power/ground/flags) and 2 types of how to display the netlabel: over wire or symbol "portal" p.s. pictures attrached here are not tscircuit.

2. Automatic placement and authoring. This is completely separate from appearance. It defines jsx syntax and heuristics on where and what should be displayed. In this case you're asking, why should we display netlabel over the wire that already has a trace clearly followed to the destination. In this example we have `t_bat_12v` wire/trace/net name and it is not clear what the semantic of this. Is this a name of the trace that goes between two chips, or there should be a junction, like a tap into other component (e.g. thermistor or a battery). So it's clearly an invalid diagram, IMHO, as schematic shouldn't be ambiguous. If this is true junction tap, there should be a junction dot going from the trace between two chips out to the "portal"/port label. If this is merely to say that this wire betwen two chips has a name, the flag symbol should not be displayed at all, replaced with a vertical or horizontal text over the wire. If you understand the semantic, you can then reason about how to represent it in jsx, circuitjson and internal hueristics in the middle.

Regarding authoring, even for nets that portal in and out on the same sheet, you probably want two explicit ways: - position multiple symbols (e.g. netlabels with symboltype="flag"), each traced to own pin/trace connection, specify x,y,connection for each - position a text that shows a label of the wire, specify only a (how far along the wire trace) and a margin (how far orthogonal to the wire). maybe x,y of the text center would suffice, but they you would need multiple text alignment nudges. Suggested syntax: <netlabel labelType={"anchor" | "text"} schAnchorX={x} schAnchorY={y} achAnchorSide={top|left|bottom|right} schAnchorSymbol={GND | VCC | ANALOG | DIGITAL} schTextPosition={distanceFromConnection} schTextGap={gapFromTrace} connection="U1.pin1" />

Once manual placement/authoring is refined, you can think about the default heuristics if none specified.

tldr summary of the thread

https://tscircuit.com/editor?#data:application/gzip;base64,H4sIAJkXa2oAA3WQzQrCMBCEX2XZk4LEn5OI7UEUUQQPIh6MSGyiDdgktBELpe/uqtXqoblN5tvZSQrURqqc+SzHEarc2dSDVGdxu3potSEIocUN0BmfrEgl3LX0ccBx0EsSjhArfYn9V4cAb5r4KNYOjEgUuUl0I/hsrXepNk8+szoa0p3TZiVO6poFRfEUwxFw3OymizWZZQndpsjlcTqbbOcNsX9jPhWRqjV8Ivwxu0ttCf/xnKD3FXuOjEoDq6p0qBWrVgKjnn2Oh7Keq/eNu6+PCrnhpo3lA6Ni9OthAQAA chip to chip label current behaviour

chip-to-chip + GND

chip-to-chip + VCC

chip-to-chip + VCC + explicit netlabel position with connectsTo=net.VCC

chip-to-chip + VCC + explicit netlabel position with connectsTo=mcu.VCC

two positioned net labels, each connecting to corresponding pin

changing anchorSide to bottom. very strange that sometimes you get different symbols

is it based on hardcoded GND net?

top/bottom achnorSide with VCC. So you can control the anchor symbol implicitly by renaming the net? But I couldn't find a way to flip the anchor, so that trace connection os from the opposite side of the flag

EDAs seem to have many more explicit concepts

Yeah, VCC and GND seems to be hardcoded nudges for the net label symbol. Every other label rotates the "digital" net port. So there are net flags: net label symbols that define a portal to the power/gnd rail. And there are net ports: net label symbols that define a portal to another place on the current sheet (or sometimes on a different sheet when page number specified). This is what I called the "portal" And there are also true net labels: net label as a text above the wire/trace.

So netport/netflag seems to be very similar concepts. The crucial difference is electric. Netflag defines the global net (PCB plane) implicitly, sort of like our `<netlabel` (possibly ignoring the `<subcircuit` namespace), while netports are local by default The netlabel vs netport differ only schematically (port label shows the direction of the signal, while label is just text). But netport can span separate sheets, while netlabel can end and start in the same subcircuit, so to speak.

So it seems in most cases we just want netlabels, sometimes going in and out of the "wormhole" on the same sheet, without any direction specifier. And in most cases (chip-to-chip connection), we don't even need neither netlabel nor port. Tscircuit seems to lack a net label as text concept and treats `<netlabel` as an alias for net port or net flag, depending on hardcoded "GND/VCC" net names.

drafted a spec, take a look: https://github.com/tscircuit/core/issues/2934

an alternative is deprecating `<netlabel>` and introducing `<netlabel2>`, `<netflag>` and `<netport>` that would have some additional implicit pcb logic, but I thinkg having `<netlabel`, `<net>` and `<trace>` is confusing already

another option to consider is introducing some flag to `<netlabel` that would tell the engine to draw `<net name` or `<trace name` as text over the wire rather than port/flag symbol.

ground types is a totally other can of worms

<@757706909351411845> related to https://discord.com/channels/1233487248129921135/1534344316779237547