# contributor·Active
Seve - This is a bug in the net label position ...
This is a bug in the net label position selection for symbols with a preferred orientation like VCC and GND with existing repros in core
Started by SeveJul 7, 202618 messages
← Back to community index
Discussion
Last active 6 days ago · plain textSeveoriginal post
This is a bug in the net label position selection for symbols with a preferred orientation like VCC and GND with existing repros in core
Seve
When the preferred orientation is up, you search for the highest corner
When the orientation is down, you search for the lowest
Seve
The GND issue is most obvious, the VCC label could go in the middle or on the left, the right side is too crowded
Abse
I'm on it , is this in core (where the fix should be) ?
Mustafa7
Schematic-trace-solver I think
Abse
ok will take a look thanks
Seve
There are examples of the bug in core but the fix is schematic trace solver
Abse
where is this image from <@757706909351411845> can we get this as a repro ?
Abse
would love to make this a repro
Seve
somewhere in core, i wish i attached the name
Seve
i wonder if ai can find the test based on the screenshot
Seve
some of your screenshots/arrows i don't understand the issues on fwiw
Abse
hmmm , so labels should be for eg GND label should be on the same level as the lowest port but not needed to be on the lowest port it self , it can be in mid between the ports ?
Abse
found it repro46
Seve
ty sry for not including the name
Abse
<@757706909351411845> https://github.com/tscircuit/core/pull/2608
Want to add to the conversation?
Reply in Discord so your notes stay connected to the source.