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I’m trying to run some experiments to see whether ML/deep learning can speed up high density solving/simplification. I think these may be closely related problems. I wanted somewhere to track all of my work, so I created this repo: https://github.com/tscircuit/al ml experiments H
i got a really good placement but the VAL messed up .
SHIBO'S BOARD IS FUNCTIONAL!!!!! https://x.com/seveibar/status/2095240476882583800?s=20
mention ‘s board arrived!!! Has messed up holes 😭
any idea on how to get really realistic code render code editor
mention mention mention etc.. i have been trying to route this board , but this stuck at some phases ,, any tips .. so that this board gets routed successfully ..
not sure how usefull but srj to video https://github.com/0hmX/srj video
mention found a really good repro, super small and tons of trace bugs https://github.com/tscircuit/ti/pull/134/files diff 6fb420e46f6876a56a2e3d3a178f2c8572dcea1df084f9823ec9c7f63f00b03e
mention check out this preview link, says error https://tscircuit.com/abse/wifi smart switch files
mention
mention no holes in your board
mention IMPLICIT COPPER POURS
for footprint="pinrow3 p2.54 id1.016 od1.88 pinlabeltextalignright pinlabelorthogonal nosquareplating" it generates a courtyard, we should add a way to change the courtyard's default dimension somehow
why do we generate both, we should jsut create .agents/ should i remove .claude/ <@&1420812538421051555
mention after fabrication the default silkscreen size of components sucks
Hey tscircuit peeps! How to fix drill file not populating? ISSUE: Drill holes not showing up in drill file when file export fabrication files & upload to JLCPCB context: im building a keyboard with @tsci/seveibar.keyboard utils WORKAROUND FIX: import and export using kicad. any t
mention this you? Did you respond?
How do you do: a thruhole with different mask on top and bottom, and different copper on top and bottom?
vercel deployment is failing mention https://github.com/tscircuit/ti/pull/214
mention these issues are blocking me from routing the AM62L board, a lot of progress was made, it's nearly there https://github.com/tscircuit/tscircuit autorouter/pull/2247 https://github.com/tscircuit/tscircuit autorouter/pull/2248 https://github.com/tscircuit/tscircuit autorout
Why does this board require maxDecouplingTraceLength="6mm" instead of the default 1 mm? Is there a way to fix the routing by repositioning the components, or is 6 mm the safest solution without significantly changing the physical layout?
Why core tests taking so much time to finish locally, literally takes hour to finish
Guys as of yesterday, schSize="sm" and schSize="xs" is available for <resistor / and <capacitor /
What is up with github?
Why was this text on components and ports introduced to the schematic trace solver test snapshots? It is making things difficult to review
I ♥️convex optimization
U guyz I have so many ideas I wanna play around with for optimizing funky bus routes
Can we introduce thermalPadNotchLeft and thermalPadNotchRight for these types of thermal pads? ehh you would need to show it's more universal i don't know if this is common if it's in IPC then we could yeah, makes sense. gotcha mention It seems too expensive and is also out of st
My ai and some of its life demands as i am building the boards! i think the erc is good!
https://github.com/tscircuit/ti/pull/120/changes the footprints are wrong for am62l needs an update its a bit smaller 0.3 dia is wrong its 0.254 dia
not seeing this when i run locally https://tscircuit.com/tscircuit/ti/releases/1a2d8fe2 3a34 468a 9557 70d7102d837b
how can i build release to publish a site ? i am getting timeout .
is this how a fanout should look like? mention
Why are these parts not available in JLCPCB? I want to make this camera module, but the required camera components are always missing from JLCPCB’s parts library. It keeps asking me to a pre built camera module instead.
Got this todayyyy !!!!! super coollll working great as expected, great work, team !! 🔥🔥
are boards that expensive
mmm
i wonder if we should switch the netlabel style to altium style net labels
multi day project to get these schematics to look basically identical
https://github.com/tscircuit/bga fanout solver
we really need to make a rockchip board for tscircuit/common, rockchip is all over my timeline
mention new page is indexing all of JLC's RAM, we can try to use one of these and connect it to anything https://jlcsearch.tscircuit.com/drams/list
mention the fanout solver can't be used with pipeline 7 right?
Most in stock WLEDs
mentioned this to mustafa already but i like courtyardwidth with "cyw" as an abbreviation when the user wants to manually specify it or we manually compute it in circuit json to footprinter
what is this error ??
mention currently footprinter supports params like w h for passives but there are courtyards being generated for custom footprinter strings for passives and also easyeda imports(string like res p4.6599mm pw2.91mm ph2.9106mm) doesnt describe the w/h in the passives strings. So is