# Review pls guys πŸ˜„ Channel: #designreview Source: https://discord.com/channels/1233487248129921135/1546848154337411162 Started: 2026-09-08T11:48:09.433000+00:00 Last activity: 2026-09-19T17:55:16.990000+00:00 ## pixalynx β€” 2026-09-14T17:01:44.746000+00:00 Its merged now, so to fix my current board do I need to give it any specific prompt ? ## Rishabh β€” 2026-09-14T17:03:36.414000+00:00 It should be upstream, you can ask ai to re-import that component. And you should see the cutout in the pcb board ## pixalynx β€” 2026-09-15T13:33:12.731000+00:00 Hey guys this is the response i got back from jlcpcb ```We have checked with our engineering team, but unfortunately, we have not found a suitable drop-in replacement for J1 (C2879827) that meets your requirements without modifying the PCB. Could you please confirm how you would like to proceed? Provide your own replacement component for us to use for assembly; or Leave J1 as DNP (not assembled). Please note that if J1 is left as DNP, the unused component will not be shipped together with the finished boards. We will not modify the PCB or force-fit the original connector without your approval. Please let us know your preferred option, and we will proceed accordingly. Thank you for your understanding and support. Best regards, Mason``` Not sure what the best way to proceed ## pixalynx β€” 2026-09-15T13:33:35.333000+00:00 should i let them modify the pcb ? ## Rishabh β€” 2026-09-15T13:52:27.761000+00:00 ask them to cancel the order. You can re-order that board with the new cutout in place, which will work ## pixalynx β€” 2026-09-15T14:05:23.279000+00:00 ok ## Seve β€” 2026-09-15T15:27:22.169000+00:00 <@809856037376491570> might not be a full refund since they already have fabricated and partially assembled, my guess is he'll get back just shipping ## Seve β€” 2026-09-15T15:27:44.225000+00:00 you could ask it to be force-fit <@174613218772254720> haha ## Seve β€” 2026-09-15T15:27:58.972000+00:00 idk ## Seve β€” 2026-09-15T15:28:06.827000+00:00 rishabh is probably right that cancelling is the best option ## Seve β€” 2026-09-15T15:28:14.409000+00:00 if they'll do it ## Rishabh β€” 2026-09-15T15:28:19.126000+00:00 Is it? I think if you nudge them couple of times they might refund the full amount ## Seve β€” 2026-09-15T15:28:27.804000+00:00 worth a try ## Rishabh β€” 2026-09-15T15:28:31.935000+00:00 yeah ## pixalynx β€” 2026-09-15T15:39:40.468000+00:00 if we go the force fit route, what are the implications ? ## Rishabh β€” 2026-09-15T15:47:50.525000+00:00 It might break or get uprooted from the pcb while plugging in the usb cable to it ## Seve β€” 2026-09-15T16:20:13.048000+00:00 i'm not sure it's possible in this case haha ## Seve β€” 2026-09-15T16:20:20.598000+00:00 they'd need to dremel the pcb ## pixalynx β€” 2026-09-15T18:15:35.117000+00:00 Hey guys can i get a review on v1.2.6 - https://tscircuit.com/pixalynx/esp32-usb-ducky#3d I think it has the usb connector better placed however in the 3d viewer there is a slight gap from the pcb edge, is this ok/expected ? ## pixalynx β€” 2026-09-15T18:22:01.217000+00:00 Also was there a new tscircuit update? my traces are looking soo much cleaner in v1.2.6 vs the v1.2.4(this is what went to jlcpcb) ## Rishabh β€” 2026-09-15T18:30:55.416000+00:00 I don't think it's still imported using the latest easyeda-converter ## Rishabh β€” 2026-09-15T18:31:06.157000+00:00 cause I don't see the cutout yet ## Rishabh β€” 2026-09-15T18:31:53.951000+00:00 or maybe it's okay ## Rishabh β€” 2026-09-15T18:35:41.273000+00:00 I think this is what expected, the usb c shouldn't be placed on top of the board rather in between the cavity. <@757706909351411845> what should we do in this case? cause the easyeda-converter has the cutout in place, but that is for the metal part. Attachment: image.png β€” https://community.tscircuit.com/media/1549488896080085122 Attachment: H3929ee6381c54de8a353fade695ccd07i.png β€” https://community.tscircuit.com/media/1549488896545525770 Attachment: image.png β€” https://community.tscircuit.com/media/1549488896948310066 ## Rishabh β€” 2026-09-15T18:36:14.946000+00:00 It looks like this still Attachment: image.png β€” https://community.tscircuit.com/media/1549489038497419284 ## pixalynx β€” 2026-09-15T18:46:15.850000+00:00 what would be the easiest fix, should i use a different usb c component ? ## pixalynx β€” 2026-09-15T18:50:05.543000+00:00 the part on jlcpcb looks like this Attachment: C2879827-E6ADA3E99DA2.png β€” https://community.tscircuit.com/media/1549492522181468230 ## Rishabh β€” 2026-09-15T18:50:28.188000+00:00 I think this is the bottom view ## pixalynx β€” 2026-09-15T18:50:51.186000+00:00 topviuew looks like this Attachment: C2879827-E58F8DE99DA2.png β€” https://community.tscircuit.com/media/1549492713542394016 ## Seve β€” 2026-09-15T20:36:25.216000+00:00 The jlcpcb cutout is correct ## Seve β€” 2026-09-15T20:37:49.301000+00:00 It is β€œplaced” on top, and rests inside the cutout cavity. Seems about right the way we’re importing it ## Rishabh β€” 2026-09-15T20:55:36.674000+00:00 we don't generate cutoout cavity though Attachment: image.png β€” https://community.tscircuit.com/media/1549524110281805945 ## Seve β€” 2026-09-15T22:35:48.320000+00:00 !! ## Seve β€” 2026-09-15T22:35:54.121000+00:00 i'm confused ## Seve β€” 2026-09-15T22:36:03.129000+00:00 it all should be part of the cutout ## Seve β€” 2026-09-15T22:36:45.891000+00:00 i'm not 100% sure that there needs to be a cutout there. Haha maybe i should stop trying to help i feel like i'm getting confused Attachment: CleanShot_2026-09-15_at_15.36.162x.png β€” https://community.tscircuit.com/media/1549549566460690463 ## pixalynx β€” 2026-09-15T23:30:19.090000+00:00 I was also thinking that was the cutout tht matced the 3d view ## pixalynx β€” 2026-09-16T00:51:51.067000+00:00 do you mean a cutout cavity on the board? ## Rishabh β€” 2026-09-16T07:57:30.527000+00:00 Yeah, I think it should be something like this, right? Attachment: 4396-03.png β€” https://community.tscircuit.com/media/1549690681973538877 ## pixalynx β€” 2026-09-16T10:22:36.182000+00:00 are you sure about that ^ ?because from the iamges it looks like it just hangs off the board 😱 ## pixalynx β€” 2026-09-16T10:22:43.568000+00:00 from the jlcpcb images ## Rishabh β€” 2026-09-16T10:26:37.687000+00:00 I think so, this is one of my board which I have sent for fab. I haven't received any complaints from the fabricator. https://tscircuit.com/imrishabh18/corne-keyboard#3d Attachment: image.png β€” https://community.tscircuit.com/media/1549728208394391603 Attachment: image.png β€” https://community.tscircuit.com/media/1549728209023664169 ## pixalynx β€” 2026-09-16T10:27:02.110000+00:00 us that a usb c male ? ## pixalynx β€” 2026-09-16T10:27:14.427000+00:00 ill just use your project and take the usb connector and put it in mine ? that should work ## Rishabh β€” 2026-09-16T10:28:48.544000+00:00 That's usb-c female, you plug a usb-c male to this ## pixalynx β€” 2026-09-16T10:29:00.523000+00:00 oh ## pixalynx β€” 2026-09-16T10:29:04.111000+00:00 mine was usb c male ## pixalynx β€” 2026-09-16T10:29:41.610000+00:00 have you guys previously sent a usb c male for fab before ? ## Rishabh β€” 2026-09-16T10:30:05.826000+00:00 I don't think so ## Rishabh β€” 2026-09-16T10:31:01.882000+00:00 Ask claude for reference kicad files for the board which you're trying to make. Or ask the ai what is the best way with the cavity or without. ## pixalynx β€” 2026-09-17T16:14:55.938000+00:00 I havent replied to them for the previous message(been busyh with work) but they just sent me this email ```We have further checked with our production team, and they have confirmed that J1 (C2879827) can be reworked. However, please note that the rework process involves certain risks to the PCB and connector, so we would like you to be aware of this before proceeding. If you would like us to proceed with the rework, please provide us with the updated and complete production files for our review and confirmation. Once we receive the updated files, we will continue to evaluate the rework arrangement and proceed accordingly. Thank you for your understanding and cooperation. Best regards, Mason``` ## Rishabh β€” 2026-09-17T16:15:48.400000+00:00 I think you can try and send the new fabrication file's and see what they say ## pixalynx β€” 2026-09-17T16:16:13.961000+00:00 ok ## pixalynx β€” 2026-09-17T16:30:02.762000+00:00 send them the new fab files, let see what they say 🀞 ## pixalynx β€” 2026-09-19T16:30:41.760000+00:00 Hey guys this was the latest update from JLCPCB ```Hi Customer, Thank you for providing the updated fabrication files. For the revised PCB design, please move the board outline to the mechanical layer (GM1), as shown in the picture below. After updating the file, please send us the revised fabrication files so we can proceed with the review. Thank you for your cooperation and support. Best regards, Mason``` Attachment: ADKq_NYQxL7GURYGf-cElP7JJw-bmabqLS8NOm9Btf3mp6fVZZ9lvo29oIIuMtUJhT7CvOBChH8kB2lmVmu_GQq2smVkfxF-4pteHRXVMUy4kNWKf2Ojj3rCCdIUUG_6fjzbj-17-5Ib92PkVVno355CpzBBwMxwKQwgCExmilTcmMtXM3_VFjQeTApKD73qupxsQ_-ZbDTVBfmfqu8mzq8Ss0-d-e1-ft.png β€” https://community.tscircuit.com/media/1550906993428926484 ## Seve β€” 2026-09-19T16:31:04.103000+00:00 ??? that's very strange ## pixalynx β€” 2026-09-19T16:31:52.872000+00:00 so the previous email i sent them the updated fab files with the usb c fix (the placement fix) ## pixalynx β€” 2026-09-19T16:33:20.540000+00:00 this all happened because i wanted a usb c male πŸ˜‚ hahahhaa i shouldve just stuck to usb a ## Seve β€” 2026-09-19T16:33:49.636000+00:00 i'm looking into it, this seems like a possible tscircuit bug i'm not really sure ## Seve β€” 2026-09-19T16:33:54.324000+00:00 i've never seen them comment this ## Seve β€” 2026-09-19T16:35:29.339000+00:00 can you upload your source code as a zip, or use the "FIle > Report Bug" feature in the viewer ## Seve β€” 2026-09-19T16:35:36.170000+00:00 also can you upload the gerbers if possible ## Seve β€” 2026-09-19T16:35:46.673000+00:00 just trying to figure out wth they're talking about ## pixalynx β€” 2026-09-19T16:37:17.020000+00:00 These were the fab files i sent, the version i sent them is a few versions back Attachment: esp32-usb-ducky_fabrication_files_4.zip β€” https://cdn.discordapp.com/attachments/1546848154337411162/1550908651433234544/esp32-usb-ducky_fabrication_files_4.zip?ex=6ab00bbc&is=6aaeba3c&hm=5d878732748fb509628decb9a8b40db4e751b666e5a9a55a3bef403e84b73ab3& ## pixalynx β€” 2026-09-19T16:37:50.152000+00:00 how do i do this ? ## Seve β€” 2026-09-19T16:38:06.341000+00:00 how do you build, do you do it in codex ## Seve β€” 2026-09-19T16:38:13.923000+00:00 if you do it in codex, ask it to run tsci dev ## pixalynx β€” 2026-09-19T16:38:32.519000+00:00 oh yes ^ let me do that ## pixalynx β€” 2026-09-19T16:40:44.916000+00:00 uhm the verison thats on my local is a few versions ahead of what i sent to jlcpcb ## Seve β€” 2026-09-19T16:42:14.635000+00:00 hmm ## Seve β€” 2026-09-19T16:42:22.187000+00:00 well i think it's fine ## pixalynx β€” 2026-09-19T16:42:23.061000+00:00 would you be able to access a previous version ? ## Seve β€” 2026-09-19T16:42:28.694000+00:00 they haven't moved your board into production yet ## Seve β€” 2026-09-19T16:42:33.086000+00:00 no whatever is fine ## Seve β€” 2026-09-19T16:42:37.498000+00:00 we're just trying to reproduce this ## pixalynx β€” 2026-09-19T16:42:43.254000+00:00 ok ## Seve β€” 2026-09-19T16:43:05.770000+00:00 btw it is a good idea if you're not already to push to a private package on tscircuit.com ## Seve β€” 2026-09-19T16:43:11.484000+00:00 that way staff can access it and help ## Seve β€” 2026-09-19T16:43:18.432000+00:00 using "tsci push" ## pixalynx β€” 2026-09-19T16:44:05.433000+00:00 oh i thought those public packages had everything including source ? ## Seve β€” 2026-09-19T16:44:16.860000+00:00 do you have a public package ## pixalynx β€” 2026-09-19T16:44:17.228000+00:00 its not the same ? ## Seve β€” 2026-09-19T16:44:19.493000+00:00 that would also be fine ## Seve β€” 2026-09-19T16:44:31.496000+00:00 found it https://tscircuit.com/pixalynx/esp32-usb-ducky#3d ## pixalynx β€” 2026-09-19T16:44:43.212000+00:00 yueah its v1.2.4 ## pixalynx β€” 2026-09-19T16:45:14.227000+00:00 hang on or it could be v1.2.5 ## pixalynx β€” 2026-09-19T16:49:34.157000+00:00 <@757706909351411845> sorry i just confirmed its v1.2.6 is what i sent ## Seve β€” 2026-09-19T17:29:57.047000+00:00 i ran the ai analysis on 1.2.4 Attachment: CleanShot_2026-09-19_at_10.29.352x.png β€” https://community.tscircuit.com/media/1550921904599334982 ## Seve β€” 2026-09-19T17:30:02.978000+00:00 i would ask your AI which might have more context ## Seve β€” 2026-09-19T17:30:13.247000+00:00 i think maybe your AI might have done something weird to export the gerbers ## Seve β€” 2026-09-19T17:30:19.753000+00:00 i don't see any obvious issues ## Seve β€” 2026-09-19T17:30:32.631000+00:00 when you uploaded gerbers, were those the jlcpcb gerbers? Or did you regenerate? ## pixalynx β€” 2026-09-19T17:40:00.083000+00:00 Can you run it on v1.2.6 because v1.2.4 is the version that went to jlcpcb for initial fab where it had the usb c placement error. v1.2.6 is the one where i re ran and it had fixed the usb type c placement and i sent the fab files via email and not through the jlcpcb ui ## Seve β€” 2026-09-19T17:43:52.205000+00:00 i think you should send the screenshot of the JLC feedback to your AI for correction ## Seve β€” 2026-09-19T17:44:08.624000+00:00 i'm not 100% sure it's a tscircuit bug since thisis the first time i've seen it ## Seve β€” 2026-09-19T17:44:19.182000+00:00 it seems more likely to me that your AI manually generated gerbers or something weird like that ## pixalynx β€” 2026-09-19T17:46:43.999000+00:00 ok let me have a look ## pixalynx β€” 2026-09-19T17:53:52.718000+00:00 ```Let me look at the actual layer files in that export to pin down what their CAM is complaining about. Inspected layer naming and outline file content Now I can explain exactly what's happening, and it's a file-naming problem, not a design problem. Your outline file is correct in content: Edge_Cuts.gbr holds the closed rectangle (x -13..13, y -49..33.25) drawn with a 0.05 mm aperture, and it even declares itself properly with the Gerber X2 attribute %TF.FileFunction,Profile,NP. Their CAM ignores that attribute and maps layers by filename, which is why the outline never reached the GM1 slot. Let me build the corrected files.``` ## pixalynx β€” 2026-09-19T17:54:27.854000+00:00 ```Corrected bundle built β€” same copper, outline now named .GM1. Updating the project's fab script so future bundles comply too, and sending you the file. Updated fab script for GM1 and rebuilt 1.2.8 bundle Sent v1.2.6 with JLC's fix applied: the exact files you already sent, with the outline renamed Edge_Cuts.gbr β†’ esp32-usb-ducky.GM1 and F_Fab.gbr removed. No copper, drill, BOM or CPL changes. ZIP esp32-usb-ducky_v1.2.6_GM1.zip 52.1KB What Mason is asking for: their CAM can't find your board outline, so they want it supplied as the mechanical layer GM1. Why it happened β€” a naming issue, not a design one: Your outline file is correct inside. Edge_Cuts.gbr holds the closed rectangle (x -13..13, y -49..33.25) drawn with a 0.05 mm aperture, and it declares itself properly with the Gerber X2 attribute %TF.FileFunction,Profile,NP. Their CAM maps layers by filename, ignoring that attribute. The screenshot's 12 rows match your 12 files exactly: to/tp/ts/tl = top silkscreen/paste/mask/copper, bl/bs/bp/bo = the bottom set, drl/npth = your two drill files. That leaves gm1 and dd for the two files their matcher didn't recognise β€” Edge_Cuts.gbr and F_Fab.gbr. So the slot they rout the board from is holding the wrong file, which is why the layer they highlighted looks nearly empty. F_Fab.gbr is worth removing rather than renaming. It's a fabrication drawing of component outlines spanning x -10..11.8, y -47.5..15.9. If an operator ever treated that as the mechanical layer, it would rout along part outlines instead of the board edge. The fix, in the file I've sent you: the exact files you already sent them, with Edge_Cuts.gbr renamed to esp32-usb-ducky.GM1 (byte-identical content, verified) and F_Fab.gbr dropped. Copper, drill, BOM and pick-and-place are untouched, so it's still the v1.2.6 design they're mid-review on β€” nothing for them to re-check but the outline.``` ## pixalynx β€” 2026-09-19T17:55:16.990000+00:00 that was the response from claude, i think its good for me to resend the newer files