# Vivek Vijayan - Is this the right approach to u...

Channel: #support
Source: https://discord.com/channels/1233487248129921135/1528676547127410738
Started: 2026-07-20T08:14:50.954000+00:00
Last activity: 2026-07-21T15:22:31.689000+00:00

## Vivek Vijayan — 2026-07-20T08:14:50.272000+00:00

Is this the right approach to use `exposedNets`
```
export const SensorFrontEnd = () => {
  return (
    <subcircuit exposedNets={["VCC","GND", "SIG_OUT"]} name={name} showAsSchematicBox={showAsSchematicBox}>
      <port name="VCC" direction="left" connectsTo={["R_p.pin1"]} />
      <port name="GND" direction="left" connectsTo={["C_f.pin2"]} />
      <port name="SIG_OUT" direction="right" connectsTo={["R_p.pin2"]} />
      <resistor name="R_p" resistance="10k" footprint="0603" />
      <capacitor name="C_f" capacitance="100nF" footprint="0603" />
      <trace name="tr_internal_sig" from=".R_p.pin2" to=".C_f.pin1" />
    </subcircuit>
  )
}
export const SignalProcessor = () => {
  return (
    <subcircuit name={name} exposedNets={["VCC","GND", "SIG_IN"]} showAsSchematicBox={showAsSchematicBox}>
      <port name="VCC" direction="left" connectsTo={["R_l.pin1"]} />
      <port name="SIG_IN" direction="left" connectsTo={["R_l.pin2"]} />
      <port name="GND" direction="right" connectsTo={["C_d.pin2"]} />

      <resistor name="R_l" resistance="1k" footprint="0402" />
      <capacitor name="C_d" capacitance="1uF" footprint="0402" />

      <trace name="tr_internal_vcc" from=".R_l.pin1" to=".C_d.pin1" />
    </subcircuit>
  )
}

export const ControlCircuitSystem = () => {
  return (
    <group name={name} showAsSchematicBox={showAsSchematicBox}>
      <SensorFrontEnd name="sensor" showAsSchematicBox={true} />
      <SignalProcessor name="processor" showAsSchematicBox={true} />

      <trace name="t_signal_bus" path={["sensor.SIG_OUT", "processor.SIG_IN"]} />
      <trace name="t_vcc_bus" path={["sensor.VCC", "processor.VCC"]} />
      <trace name="t_gnd_bus" path={["sensor.GND", "processor.GND"]} />

      <port name="SYS_VCC" direction="left" connectsTo={["sensor.VCC"]} />
      <port name="SYS_GND" direction="left" connectsTo={["sensor.GND"]} />
      
    </group>
  )
}
```

## Vivek Vijayan — 2026-07-20T13:25:29.744000+00:00

I found the mistake. Instead of `exposeNets` boolean, I was using `exposedNets` string[]. Now I can connect subcircuits with each other. Still schematic view is buggy. 
In the code, there is a connection between lvps.SEC_GND and mcu.GND. But it is not rendering properly. 
```
{/* Power: LVPS 3.3V to MCU 3.3V */}
        <trace name="t_v3v3_link" path={[".lvps > .VOUT_3V3", ".mcu > .3V3"]} />
        <trace name="t_gnd_link" path={[".lvps > .SEC_GND", ".mcu > .GND"]} />
```
Also the ports are assigned with name <subcircuit_name>_connectivity_net<number>
Attachment: image.png — https://community.tscircuit.com/media/1528754725971824751

## Seve — 2026-07-20T14:40:59.818000+00:00

Yea that is awful- cc <@1079361271687807026> (we must never manipulate names!)

## Mustafa7 — 2026-07-21T14:16:09.959000+00:00

<@757706909351411845> isnt this repro https://github.com/tscircuit/core/pull/2735/files same as above circuit? you meant to fix the connectivity net names leaking right?

## Mustafa7 — 2026-07-21T14:17:16.486000+00:00

The fix is the remove those netlabels right?https://github.com/tscircuit/core/pull/2738
Can you please clarify

## Seve — 2026-07-21T14:18:31.590000+00:00

The visual snapshot needs explatory text

## Seve — 2026-07-21T14:18:59.274000+00:00

Assume the viewer cant see the test code- because you repro’d separately i literally cannot

## Seve — 2026-07-21T14:19:15.716000+00:00

It is impossible to review!!!! I have no idea what im seeing!!

## Mustafa7 — 2026-07-21T14:23:10.767000+00:00

i'll create a separate repro and tag you

## Seve — 2026-07-21T14:23:18.406000+00:00

If i expand test content i can see the code

## Seve — 2026-07-21T14:23:49.767000+00:00

But the visual snapshot needs explanatory text IN the schematic snapshot

## Seve — 2026-07-21T14:24:21.281000+00:00

So it is possible to review if i expand code on github

## Mustafa7 — 2026-07-21T14:24:35.193000+00:00

https://github.com/tscircuit/core/pull/2742

## Mustafa7 — 2026-07-21T14:35:44.684000+00:00

Closing as i think the behaviour might be correct, confusing and difficult to understand for now, Let me know if these "...connectivity_net0" etc netlabels are correct behaviour.

## Seve — 2026-07-21T15:06:37.321000+00:00

The connectivity net id net labels are not the correct behavior

## Seve — 2026-07-21T15:07:25.142000+00:00

For my review- i was commenting on your schematic text, it doesnt describe the issue

## Mustafa7 — 2026-07-21T15:22:31.689000+00:00

<@757706909351411845>