# astrimid - Am I not getting something or is it ...

Channel: #support
Source: https://discord.com/channels/1233487248129921135/1525727760956526652
Started: 2026-07-12T04:57:25.929000+00:00
Last activity: 2026-07-13T02:29:55.897000+00:00

## astrimid — 2026-07-12T04:57:24.863000+00:00

Am I not getting something or is it a known limitation?

https://tscircuit.com/editor?template=blank-circuit-board#data:application/gzip;base64,H4sIAGodU2oAA7WSXUsrMRCG/0rIlYKN27V76hFXOBxBvBGt4o2RJW7HurI7WZJUKqX/3cl+tLWtWoTuzSYz77x5Mpkpz3AIE+HshJ/wrCi1cWwAKnXs2eiCSW78RnKJEmFSpVON1rE7sO5Wj00KlsVsb5/FZ2xPImOnI6PH5Zlf0samL1Aol6UWUpdpZKgKiCW3dank7JCkjRjBtfnz/8nlVZNdzV1cnX+ue9O5UyOoPVvVfdJ6NOl4GgYzRkAD7YhIYzzt/KXI/IjNNtG6T/SVzYI1V0+QM1os3YUah3UXKCgaPibKDLuUVZi+aHObDf2pTpcrl/9sGG10bFB/smxMnVGLa1abZIRD0viXXyUMKe40RYlALB7gG6No2WmZ7Eur08N2dPYl8gNeKByrvAPDzFnxajXSiE69kManHaukzOm8AtDRLJ2whxqpUvmPlJBTh7TxWcmvB2FAnTlY5FMqhSo7L/LhiY90+uLPXOqj7z4aibCNzZaMDOQE9AaJ0/VZ1WWS1r8WtgXfAlLntgXsif4mwN5OAbv97QFD0dsE2N1tB4PtAQNxvA7YE0e7A7wJg6N/WwMG63Rdcfx7Ov97lDjjsw8j6oY+/AUAAA==

Why wouldn't flag labels be consistent? Can't move them manually either. Is it some strange use case? I just want two voltage sources injected. Seems pretty basic to me?
Attachment: image.png — https://cdn.discordapp.com/attachments/1353415621995397172/1525727761124294656/image.png?ex=6a566a74&is=6a5518f4&hm=b63edba4011eb4f36e46a4aaff62ead58ea0118ef09a9cbd1e2cfa597094fa62&
Attachment: image.png — https://cdn.discordapp.com/attachments/1353415621995397172/1525727761593794700/image.png?ex=6a566a75&is=6a5518f5&hm=90d1991ca7248e9a39d72caa18483edb5c8dcc793d5165de05446df1bd2253e7&

## Seve — 2026-07-12T05:00:26.335000+00:00

Just o understand, you want the netlabels there is that right?

## Seve — 2026-07-12T05:00:55.562000+00:00

If you simply omit them, does that get you something desirable?

## Seve — 2026-07-12T05:02:16.471000+00:00

One of your nets is effectively given two names i think- i may be wrong. Also generally we just omit manual netlabel elements, unless you want it for some reason (placement?)

## astrimid — 2026-07-12T05:08:59.163000+00:00

long names are also truncated
Attachment: image.png — https://cdn.discordapp.com/attachments/1525727760956526652/1525730673002942585/image.png?ex=6a566d2b&is=6a551bab&hm=bb2e49d19943dd8640fafc6d82bc574ec8b877ed83aac0d8f53134a1d3c655a5&

## astrimid — 2026-07-12T05:10:02.531000+00:00

is it because there's some hardcoded distance between elements?

## Seve — 2026-07-12T05:10:11.564000+00:00

No its outside the bounds of the svg

## Seve — 2026-07-12T05:10:39.634000+00:00

This is an “svg not being expanded to full text extent issue” cc <@1507703667237716221>

## astrimid — 2026-07-12T05:14:53.546000+00:00

for now I just want a comon GND symbol below two voltage sources and connecting them to corresponding buses.

https://tscircuit.com/editor?template=blank-circuit-board#data:application/gzip;base64,H4sIAHQiU2oAA7WTUU/CMBSF/0rTJ0mgdIMJEkZixBhfiCLhxZplGVec2VqyFoIh/HfbjSG6SWbMnrbec+7tt7PcHQ75ArZEyS0e4DBeiUShKfiBQq+JiBHDiTkwzDjjsE3lQHCp0AykehLrJACJXHTRQO4IXTCO0HCZiPVqZF71QQZvEPsqDCQEKhQccT8Gl2GZtTKM2tp6MHNQuT65nVkHsUSyv/dtRKT8JWQzc9vcpt74RhsPqruz6R5pnqlQGkhwd9e60pX8irOznB+jnN8mFXHvJuMT2mE7j6fBOG7i2OdrP2rBIlSSvEvB9W/YGaOOKI/OW0V+ADFwpfMaoOfsjtSVgmMJkU5XJEZl+GFqU51d80sPdCuk6rHJlLem0uqRy6PVVD9M1SF2XtufDEog0kAb8JTI7ko/xsvnZ8a84SygUx2wS3plgN1aAa1edUCbdMsArXoTpNUBKekXAbukUx/go00715UBaZHOIv366NJ19u4nlQFt4hQRaZ0Bzv9ISMuWpGX9Z0vM44XxPd5/As7zcWgmBgAA
Attachment: image.png — https://cdn.discordapp.com/attachments/1525727760956526652/1525732159883841537/image.png?ex=6a566e8d&is=6a551d0d&hm=00f79b4f5c2bf0f340f25c6b52140e5e530c5db9662141f928bd895152ca9d19&

## astrimid — 2026-07-12T05:15:25.572000+00:00

should I use pinheader instead?

## astrimid — 2026-07-12T05:15:56.305000+00:00

are there any hello world examples for power supply schematics?

## Seve — 2026-07-12T05:16:30.598000+00:00

https://docs.tscircuit.com/guides/spice-simulation/Passive%20Filters/high-pass-filter

## Seve — 2026-07-12T05:16:31.855000+00:00

maybe

## Seve — 2026-07-12T05:17:05.345000+00:00

[attachment]
Attachment: image.png — https://cdn.discordapp.com/attachments/1525727760956526652/1525732711967494255/image.png?ex=6a566f11&is=6a551d91&hm=1bdfb5d6fcf02559421fc69eb5808428a39dbea7bbba678e7476d696193f808f&

## Seve — 2026-07-12T05:17:17.242000+00:00

https://tscircuit.com/editor?&snippet_type=board#data:application/gzip;base64,H4sIAFojU2oAA7WTUU/CMBDHv0rTJ0igdIMJEkdixBhfiCLhxZplGRVntpashWAI393rxhBlLjNmT1vv7n/36/3THQ7Fgm+JVls8xGG8kolGU+4HGr0mMkYMJ+bAMBNM8G2aDqRQGs240k9ynQRcIRc1msgdoQYTCF0tE7lejcwvHFTwxmNfh4HigQ6lQMKPucuwyqQMow6UHooF13l+cjuzDsmClP1dt5GR9pc865mXzW3qjW+g8JB1dzbdI+CZSg1AUri79iVE8hGlvZwfrZzfOp3j3k3GpxfRiQ99zXKPjGQVCnMjLSEESlIqMSglitSCTu5BkwncwrEv1n7U5otQK/KupACvd6YQfMj98VYRTIm50GDKED1ns9OqdDtY8QgslInJMvwwtSkY1PrKByDlafYoMuGtibT75OJYaqIfJuoQO4/tTxolPAKgDfe0zGall/Hy/llhLigFdKoD9ki/CLBXK6DVrw5ok14RoFXvBml1QEoG54A90q0P8NGm3evKgPScziKD+ujSh+rdTyoD2sQ5R6R1LnD+R0Ja9Eja1n9eifm8MLHH+0/g/tIXiwYAAA==

## astrimid — 2026-07-12T05:17:35.886000+00:00

it's not only SVG being truncated, the label lenghh doesn't influence the distance between components

## Seve — 2026-07-12T05:18:10.450000+00:00

yes we don't yet have refdes symbols influence the automatic packing of symbols that is true

## Seve — 2026-07-12T05:18:19.524000+00:00

i also don't think you can explicitly add a margin

## astrimid — 2026-07-12T05:18:19.710000+00:00

Yeah, the GND part is working. I just need to figure out how to inject power to network and display them

## Seve — 2026-07-12T05:18:22.644000+00:00

CC <@1079361271687807026>

## Seve — 2026-07-12T05:18:58.868000+00:00

you're trying to run a analog simulation is that right?

## astrimid — 2026-07-12T05:19:13.032000+00:00

yes, you guessed right

## Seve — 2026-07-12T05:19:13.401000+00:00

https://docs.tscircuit.com/elements/analogsimulation

## astrimid — 2026-07-12T05:38:12.849000+00:00

Here's a full example I'm working on:

For now, I'm just trying to reproduce the schematic.
If I produce the full network on a single page, it's even more illegible. So I'm trying to split into groups. But I keep fighting with label placement and long names overlapping with schematic or with other labels. Manual label placement doesn't work, as I can't drag them.
Attachment: image.png — https://cdn.discordapp.com/attachments/1525727760956526652/1525738027866132510/image.png?ex=6a567404&is=6a552284&hm=e539c7a3073311456e497b3fae60e440d1e0adcdc3ef046c53042f49e871cc83&
Attachment: image.png — https://community.tscircuit.com/media/1525738028188831804

## astrimid — 2026-07-12T05:42:55.109000+00:00

the injectable sources labels are also  inconsistent
Attachment: image.png — https://cdn.discordapp.com/attachments/1525727760956526652/1525739212156964964/image.png?ex=6a56751f&is=6a55239f&hm=8080f65538359aacf0aa1c003e79c91da9a836df52168ff01e93dccb8506a21b&

## Seve — 2026-07-12T05:44:00.389000+00:00

^^ CC <@1079361271687807026> 

You definitely need to make sure name is defined for every trace, some of those names are really long as well 🤔

## Seve — 2026-07-12T05:44:36.518000+00:00

<@1079361271687807026> check out his reference schematic on the right- we should be able to create clean reference schematics like that

## Seve — 2026-07-12T05:44:48.144000+00:00

we might need a property like hideNetLabel to avoid cluttering

## astrimid — 2026-07-12T05:45:05.264000+00:00

it seems the node placement only allows for 3 symbol names

## Seve — 2026-07-12T05:45:15.077000+00:00

<@1525187702029549659> fwiw you will need to use schX/schY to set the positions of symbols for a schematic with that level of complexity- you may already have discovered this

## Seve — 2026-07-12T05:45:33.002000+00:00

> node placement only allows for 3 symbol names

Hmm i don't follow

## astrimid — 2026-07-12T05:45:44.448000+00:00

yeah, I'm trying, but those flags won't budge

## Seve — 2026-07-12T05:46:12.141000+00:00

yea the net labels are basically always automatic right now-

## Seve — 2026-07-12T05:46:15.583000+00:00

it is an issue

## astrimid — 2026-07-12T05:46:40.819000+00:00

here, only V_V or V_3 part of the name fit
Attachment: image.png — https://community.tscircuit.com/media/1525740158887006340

## Seve — 2026-07-12T05:46:44.910000+00:00

Mustafa has been able to create a lot of schematics that match references but i'm not sure what his magic is

## Seve — 2026-07-12T05:47:12.872000+00:00

yea i think until we adjust the algorithm to pack those properly your only hope is to use schX/schY on each <voltagesource

## astrimid — 2026-07-12T05:50:57.007000+00:00

Is this the way to do?

```
import manualEdits from "./manual-edits.json";

export const PowerPathControl = () => (
  <board routingDisabled manualEdits={manualEdits}>
```

The positions seem to reset after I press run

## Seve — 2026-07-12T05:53:00.801000+00:00

We are mostly deprecating manualEdits, but it may work- schX/schY props work for all symbols and are our current recommendation

## astrimid — 2026-07-12T06:14:41.809000+00:00

hm. why does schX and  schY coordinate system start with negative numbers? I would expect 0,0 to be top left

## Mustafa7 — 2026-07-12T06:17:05.099000+00:00

Is this auto-placed?

## astrimid — 2026-07-12T06:17:19.515000+00:00

yes

## Mustafa7 — 2026-07-12T06:17:35.995000+00:00

Ok will try to fix it thanks

## Mustafa7 — 2026-07-12T06:33:39.870000+00:00

<@1525187702029549659> I couldnt reproduce the issue, this is the result with autolayout.
Attachment: Screenshot_2026-07-12_at_12.02.32_PM.png — https://community.tscircuit.com/media/1525751983296745613

## Mustafa7 — 2026-07-12T06:34:10.800000+00:00

```export default () => (
  <board width="10mm" height="10mm">
    <voltagesource name="V_V3_LONG" voltage="5V" connections={{ pin1: "net.VCC", pin2: "net.GND"}} />
    <voltagesource name="V_V3_LONG1" voltage="0V" connections={{ pin1: "net.VCC", pin2: "net.GND"}}/>
    <voltagesource name="V_V3_LONG2" voltage="3V" connections={{ pin1: "net.VCC", pin2: "net.GND"}}/>
    
  </board>
)```

## astrimid — 2026-07-12T06:42:52.854000+00:00

```
import React from "react"

export const TestSources = () => (
  <group>
    <schematicsection name="sources" />

    <net name="NET20" />
    <net name="NET5" />
    <net name="NET3" />
    <net name="NET1" />
    
    <netlabel net="NET20" anchorSide="left" connection=".V20_DC_VERY_LONG_NAME .pin1"/>
    <netlabel net="NET5" anchorSide="left" connection=".V5_DC_DC_VERY_LONG_NAME .pin1" />
    <netlabel net="NET3" anchorSide="left" connection=".V3_DC_DC_VERY_LONG_NAME .pin1" />
    <netlabel net="NET1" anchorSide="left" connection=".V1_DC_DC_VERY_LONG_NAME .pin1" />

    <voltagesource name="V20_DC_VERY_LONG_NAME" voltage={20} schRotation={-90} schSectionName="sources" />
    <voltagesource name="V5_DC_DC_VERY_LONG_NAME" voltage={5} schRotation={-90} schSectionName="sources" />
    <voltagesource name="V3_DC_DC_VERY_LONG_NAME" voltage={3} schRotation={-90} schSectionName="sources"/>
    <voltagesource name="V1_DC_DC_VERY_LONG_NAME" voltage={1} schRotation={-90} schSectionName="sources"/>

    <net name="GND" />
    <trace from="V20_DC_VERY_LONG_NAME.pin2" to="net.GND" />
    <trace from="V5_DC_DC_VERY_LONG_NAME.pin2" to="net.GND" />
    <trace from="V3_DC_DC_VERY_LONG_NAME.pin2" to="net.GND" />
    <trace from="V1_DC_DC_VERY_LONG_NAME.pin2" to="net.GND" />

  </group>
)
```

## astrimid — 2026-07-12T06:43:19.980000+00:00

I don't know what influences the distance between components
Attachment: image.png — https://community.tscircuit.com/media/1525754415955578950

## astrimid — 2026-07-12T06:43:47.356000+00:00

could it be default schematic sheet size?

## astrimid — 2026-07-12T06:45:17.502000+00:00

with schrotation and schsection removed:
Attachment: image.png — https://community.tscircuit.com/media/1525754908878569522

## astrimid — 2026-07-12T06:47:58.555000+00:00

when the label size vary, the distance seem to be preserved:
Attachment: image.png — https://community.tscircuit.com/media/1525755584505446490

## astrimid — 2026-07-12T06:48:28.839000+00:00

could it be that label width calculated incorrectly?

## astrimid — 2026-07-12T06:48:56.275000+00:00

do you even see this issue on your side?

## anil — 2026-07-12T06:49:39.185000+00:00

Hey <@1525187702029549659> , we’ve identified the issue and are currently working on it. It should be fixed soon.

## anil — 2026-07-12T06:50:53.203000+00:00

Yes, we found the issue where it is.

## Mustafa7 — 2026-07-12T06:56:03.818000+00:00

Ok so this is the bounds issue from circuit-to-svg? <@1507703667237716221> ?

## Mustafa7 — 2026-07-12T07:01:03.966000+00:00

```import React from "react"

export const TestSources = () => (
  <group>
    <schematicsection name="sources" />

    <voltagesource name="V20_DC_VERY_LONG_NAME" voltage={20}  schSectionName="sources" />
    <voltagesource name="V5_DC_DC_VERY_LONG_NAME" voltage={5}  schSectionName="sources" />
    <voltagesource name="V3_DC_DC_VERY_LONG_NAME" voltage={3}  schSectionName="sources"/>
    <voltagesource name="V1_DC_DC_VERY_LONG_NAME" voltage={1}  schSectionName="sources"/>

    <trace from="V20_DC_VERY_LONG_NAME.pin2" to="net.GND" />
    <trace from="V5_DC_DC_VERY_LONG_NAME.pin2" to="net.GND" />
    <trace from="V3_DC_DC_VERY_LONG_NAME.pin2" to="net.GND" />
    <trace from="V1_DC_DC_VERY_LONG_NAME.pin2" to="net.GND" />
    
    <trace from="V20_DC_VERY_LONG_NAME.pin1" to="net.NET20"/>
    <trace from="V5_DC_DC_VERY_LONG_NAME.pin1" to="net.NET5" />
    <trace from="V3_DC_DC_VERY_LONG_NAME.pin1" to="net.NET3" />
    <trace from="V1_DC_DC_VERY_LONG_NAME.pin1" to="net.NET1" />

  </group>
)``` 
You caould assign nets using <trace/> as well fwiw.
Attachment: Screenshot_2026-07-12_at_12.30.56_PM.png — https://community.tscircuit.com/media/1525758878573138121

## astrimid — 2026-07-12T07:10:51.978000+00:00

<@1079361271687807026> this look way better than netlabel. Any way I could change anchorSide?

## Mustafa7 — 2026-07-12T07:12:07.157000+00:00

WIth traces you cannot change anchorside, its only changeable with manual <netlabel/>

## astrimid — 2026-07-12T07:13:54.739000+00:00

so netlabel + schX/Y + achorSide?  Any way netlabel schX/Y to be calculated automatically?

## Mustafa7 — 2026-07-12T07:15:09.840000+00:00

No ig manual netlables are not calculated automatically only traces

## astrimid — 2026-07-12T07:25:27.333000+00:00

```import React from "react"

export const TestSources = () => (
  <group>
    <net name="NET20" />
    <net name="NET5" />
    <net name="NET3" />
    <net name="NET1" />

    <netlabel
      net="NET20"
      anchorSide="bottom"
      connection=".V20 .pin1"
      schX="1"
      schY="1"
    />
    <netlabel
      net="NET5"
      anchorSide="bottom"
      connection=".V5_DC_VERY_LONG_NAME .pin1"
      schX="2"
      schY="1"
    />
    <netlabel
      net="NET3"
      anchorSide="bottom"
      connection=".V3_DC_VERY_LONG_NAME .pin1"
      schX="3"
      schY="1"
    />
    <netlabel
      net="NET1"
      anchorSide="bottom"
      connection=".V1_DC_VERY_LONG_NAME .pin1"
      schX="4"
      schY="1"
    />

    <voltagesource name="V20" voltage={20} schRotation="-90" schX="1" schY="0" />
    <voltagesource name="V5_DC_VERY_LONG_NAME" voltage={5} schRotation="-90" schX="2" schY="0" />
    <voltagesource name="V3_DC_VERY_LONG_NAME" voltage={3} schRotation="-90" schX="3" schY="0" />
    <voltagesource name="V1_DC_VERY_LONG_NAME" voltage={1} schRotation="-90" schX="4" schY="0" />

    <net name="GND" />
    <trace from="V20.pin2" to="net.GND" />
    <trace from="V5_DC_VERY_LONG_NAME.pin2" to="net.GND" />
    <trace from="V3_DC_VERY_LONG_NAME.pin2" to="net.GND" />
    <trace from="V1_DC_VERY_LONG_NAME.pin2" to="net.GND" />
  </group>
)
```
Attachment: image.png — https://community.tscircuit.com/media/1525765016211689683

## astrimid — 2026-07-12T07:26:38.642000+00:00

So, this is manual placement. Is there any way I could increase the grid size without changing the schX?

## astrimid — 2026-07-12T07:32:33.558000+00:00

GND gets split as I pull nodes apart
Attachment: image.png — https://community.tscircuit.com/media/1525766804147011685

## Mustafa7 — 2026-07-12T07:38:39.129000+00:00

I am trying to fix the autolayout to consider the names

## Mustafa7 — 2026-07-12T08:25:33.003000+00:00

Is the real use cases use this lengthy names: "V5_DC_VERY_LONG_NAME"?

## Mustafa7 — 2026-07-12T08:29:45.176000+00:00

I dont think so right?

## astrimid — 2026-07-12T12:33:05.527000+00:00

For this specific case not really, but consider I'd like to put out the resistor specification on a schematic, say "300k_0402_5%" or the name the signal as `${BUSNAME}_${SIGNAL}_${DIRECTION}` to specify what controller it's coming from, what the pin name is and whther it's a sensing or a control signal, eg. VBUS2_ECOK_IN

## astrimid — 2026-07-12T12:35:47.949000+00:00

It would be ok if the component label displayed vertically, like the net labels, but I can't find the option to rotate the label

## Mustafa7 — 2026-07-12T12:49:44.860000+00:00

VBUS2_ECOK_IN will work and won't overlap

## Mustafa7 — 2026-07-12T12:50:54.392000+00:00

It's just that very long names are not handled well currently like "V20_DC_VERY_LONG_NAME" these type of long names

## astrimid — 2026-07-12T12:55:01.488000+00:00

so, is there a limit of number of characters that are handled? BTW, I've just discovered the show grid option. Still strange numbering I would say, but at least I can see the coordinates:

VBUS2_EC_OK_IN still overlaps with autorouting
```
import React from "react"

export const TestSources = () => (
  <group>
    <schematicsection name="sources" />

    <net name="NET20" />
    <net name="NET5" />
    <net name="NET3" />
    <net name="NET1" />
    
    <trace from="VBUS2_ECOK_IN.pin1" to="net.NET20" />
    <trace from="VBUS3_ECOK_IN.pin1" to="net.NET5" />
    <trace from="VBUS4_ECOK_IN.pin1" to="net.NET3" />
    <trace from="VBUS5_ECOK_IN.pin1" to="net.NET1" />

    <voltagesource name="VBUS2_ECOK_IN" voltage={20} schRotation={-90} schSectionName="sources" />
    <voltagesource name="VBUS3_ECOK_IN" voltage={5} schRotation={-90} schSectionName="sources" />
    <voltagesource name="VBUS4_ECOK_IN" voltage={3} schRotation={-90} schSectionName="sources"/>
    <voltagesource name="VBUS5_ECOK_IN" voltage={1} schRotation={-90} schSectionName="sources"/>

    <net name="GND" />
    <trace from="VBUS2_ECOK_IN.pin2" to="net.GND" />
    <trace from="VBUS3_ECOK_IN.pin2" to="net.GND" />
    <trace from="VBUS4_ECOK_IN.pin2" to="net.GND" />
    <trace from="VBUS5_ECOK_IN.pin2" to="net.GND" />

  </group>
)
```
Attachment: image.png — https://community.tscircuit.com/media/1525847955297271838

## Mustafa7 — 2026-07-12T12:56:27.053000+00:00

Yep will fix the overlaps

## astrimid — 2026-07-12T12:57:41.264000+00:00

So the 0,0 coordinate is dynamic as the schematic grows, so I should really specify all the coordinates with manual route, as automatic placement will mess up with coordinates

## astrimid — 2026-07-12T12:59:55.371000+00:00

E.g. if I just want to move just one volatage source lower, the coordinates I target will change as the schematic will try to find a new center and my schX/Y will be targeting a moving goalpost

## Mustafa7 — 2026-07-12T13:02:06.806000+00:00

If you want to use mix of auto and manual placement then use schx/schY for component you want to place manually and use schAutoLayoutEnabled prop on board element.

## Seve — 2026-07-12T15:34:40.962000+00:00

<@1079361271687807026> schAutoLayoutEnabled should be on by default!

## Mustafa7 — 2026-07-12T19:41:02.880000+00:00

So whenever someone uses schX/schY the auto layout turned off for all the components, we would want it to be on by default right so that user won't have to pass schAutoLayoutEnabled={true} when using mixed layout?
<@757706909351411845>

## Seve — 2026-07-12T19:41:14.849000+00:00

yea, it should just be on

## Mustafa7 — 2026-07-12T19:41:23.825000+00:00

Sg!

## Seve — 2026-07-12T19:41:24.929000+00:00

the auto layout used to be super broken, that's why it's off by default

## Seve — 2026-07-12T19:41:37.578000+00:00

but we need to start fixing auto layout etc so best to turn it on

## astrimid — 2026-07-13T02:29:55.897000+00:00

To summarise the thread, auto layout doesn't work very well wrt label placement, so you need to use schX/schY. <netlabel> also support X/Y positionining. schMaxTraceDistance controls how far the nodes should be located so that nets are split into separate netlabels. schX/schY coordinate system uses cartesian: `-infinity` at the top, `+infinity` at the bottom, `-infinity` to the left, `+infinity` to the right

```
import React from "react"

export const TestSources = () => (
  <board routingDisabled schMaxTraceDistance={1}>
    <net name="DC_IN" />
    <net name="GND" />
    <net name="DC5_IN" />

    <voltagesource
      name="V_DC_IN"
      voltage={20}
      schRotation={0}
      schX={2}
      schY={2}
    />
    <voltagesource
      name="V5_DC_IN"
      voltage={5}
      schRotation={0}
      schX={2}
      schY={0.5}
    />

    <netlabel net="DC_IN" connection=".V_DC_IN .pin1" anchorSide="bottom" />
    <netlabel net="DC5_IN" connection=".V5_DC_IN .pin1" anchorSide="bottom" />
    <netlabel
      net="GND"
      connection=".V5_DC_IN .pin2"
      anchorSide="top"
      schX={3}
      schY={0.3}
    />

    <trace name="trace_v" from=".V_DC_IN .pin1" to="net.DC_IN" />
    <trace name="trace_v5" from=".V5_DC_IN .pin1" to="net.DC5_IN" />
    <trace name="trace_gnd" from=".V_DC_IN .pin2" to="net.GND" />
    <trace name="trace_gnd5" from=".V5_DC_IN .pin2" to="net.GND" />
  </board>
)
```
Attachment: image.png — https://community.tscircuit.com/media/1526053033270841505