# Abse - I added some new stuff of the https://ca...

Channel: #contributor
Source: https://discord.com/channels/1233487248129921135/1511055730118230177
Started: 2026-06-01T17:16:00.430000+00:00
Last activity: 2026-06-21T11:24:36.766000+00:00

## Abse — 2026-06-01T17:16:00.118000+00:00

I added some new stuff to the https://cad-component-viz.vercel.app/ check it out

## Seve — 2026-06-01T18:11:54.630000+00:00

it looks really good!

## Seve — 2026-06-01T18:12:04.398000+00:00

definitely should be useful!

## Abse — 2026-06-03T14:36:33.799000+00:00

<@757706909351411845> wdyt about this https://docs-git-fork-abse2001-main-tscircuit.vercel.app/contributing/contributing-autorouting-dataset

## Abse — 2026-06-03T14:36:48.882000+00:00

let me know if it's messing something or something is not correct

## Seve — 2026-06-03T15:00:34.964000+00:00

This is a good start but it needs a lot more references, link to the bootstrapping repos and dataset guidelines rather than including all the information in the doc

## Seve — 2026-06-03T15:00:51.271000+00:00

Also add more details about adding a fixture with the dataset to the autorouting repo

## Seve — 2026-06-03T15:01:01.086000+00:00

Otherwise looking good, getting there

## Abse — 2026-06-03T15:11:25.835000+00:00

also do you want the BGA datasets on there own repos ?
Attachment: image.png — https://community.tscircuit.com/media/1511749155972845810

## Abse — 2026-06-03T15:11:28.471000+00:00

<@757706909351411845>

## Abse — 2026-06-03T15:44:16.569000+00:00

also can you check the component detection and topology generatioan for nested qfp components https://capacity-node-autorouter-git-fork-abse2001-qfp-tscircuit.vercel.app/?fixtureId=%7B%22path%22%3A%22fixtures%2Fbenchmarks%2Fdataset-srj18.fixture.tsx%22%7D

## Abse — 2026-06-03T17:51:10.773000+00:00

<@757706909351411845>

## Abse — 2026-06-03T17:51:30.383000+00:00

https://capacity-node-autorouter-git-fork-abse2001-qfp-tscircuit.vercel.app/?fixtureId=%7B"path"%3A"fixtures%2Fbenchmarks%2Fdataset-srj18.fixture.tsx"%7D

## Abse — 2026-06-03T17:51:44.572000+00:00

if you check sample 8

## Abse — 2026-06-03T17:52:42.760000+00:00

we have a passive components under qfp issue not sure how to handel  them

## Seve — 2026-06-03T18:16:08.042000+00:00

hello sorry for the delay

## Seve — 2026-06-03T18:16:47.881000+00:00

<@398467566588264449> the QFP topology generation looks really good?

## Seve — 2026-06-03T18:17:06.959000+00:00

do we know if this has any impact on performance (hopefully good) or on benchmark?

## Abse — 2026-06-03T18:17:55.713000+00:00

yes

## Abse — 2026-06-03T18:18:03.340000+00:00

we Improved one board

## Abse — 2026-06-03T18:18:06.224000+00:00

and failing in one

## Abse — 2026-06-03T18:18:17.532000+00:00

so no change but I'm working on a fix for the failling one

## Abse — 2026-06-03T18:19:17.040000+00:00

https://github.com/tscircuit/tscircuit-autorouter/pull/1332

## Abse — 2026-06-03T18:19:42.364000+00:00

the failling sample is 8 in the srj18

## Abse — 2026-06-03T18:20:15.376000+00:00

it fail for the passive components on top of the QFP

## Abse — 2026-06-05T15:04:03.679000+00:00

<@757706909351411845> how is this https://docs-isjj0nxcm-tscircuit.vercel.app/contributing/contributing-autorouting-dataset

## Abse — 2026-06-05T15:17:15.361000+00:00

https://github.com/tscircuit/dataset-srj19/pull/1

## Abse — 2026-06-14T14:06:20.181000+00:00

<@757706909351411845> can we merge this ?
https://github.com/tscircuit/docs/pull/700

## Abse — 2026-06-14T14:06:50.933000+00:00

I can't merge

## Abse — 2026-06-14T17:12:30.932000+00:00

also this is needed for footprinter 
https://github.com/tscircuit/kicad-to-circuit-json/pull/139

## Abse — 2026-06-14T17:12:36.560000+00:00

<@757706909351411845>

## Abse — 2026-06-17T07:33:46.525000+00:00

<@757706909351411845> can I get a review?

## Abse — 2026-06-17T07:33:47.319000+00:00

https://github.com/tscircuit/system-diagram-proposal/pull/1

## Seve — 2026-06-17T07:39:27.690000+00:00

Some images failing for me but the first 6 are good

## Seve — 2026-06-17T07:41:49.790000+00:00

You probably need some simple ones and some different styles 🤔 a lot of system diagrams are pretty simple flowchart-ish things. Eg

But i think this is pretty good
Attachment: image0.jpg — https://community.tscircuit.com/media/1516709440475365566

## Seve — 2026-06-17T07:48:47.025000+00:00

Now u gotta generate them

## Abse — 2026-06-18T11:23:10.862000+00:00

hey <@757706909351411845>

## Abse — 2026-06-18T11:23:19.920000+00:00

```
const antennaPoints = [
  { x: 0, y: 0 },
  { x: 9, y: 0 },
  { x: 9, y: 2.6 },
  { x: 3, y: 2.6 },
  { x: 3, y: 5.2 },
  { x: 9, y: 5.2 },
  { x: 9, y: 7.8 },
  { x: 3, y: 7.8 },
  { x: 3, y: 10.4 },
  { x: 9, y: 10.4 },
  { x: 9, y: 13 },
]

const traceWidth = 0.45

const antennaSegments = antennaPoints.slice(0, -1).map((start, index) => {
  const end = antennaPoints[index + 1]
  const horizontal = start.y === end.y

  return {
    pcbX: (start.x + end.x) / 2,
    pcbY: (start.y + end.y) / 2,
    width: horizontal ? Math.abs(end.x - start.x) + traceWidth : traceWidth,
    height: horizontal ? traceWidth : Math.abs(end.y - start.y) + traceWidth,
  }
})

export default () => (
  <board width="18mm" height="24mm">
    <chip
      name="ANT1"
      pcbX={-6}
      pcbY={-8}
      pinLabels={{
        pin1: ["ANT"],
      }}
      pinAttributes={{
        pin1: { providesSignal: true },
      }}
      footprint={
        <footprint>
          <smtpad
            portHints={["pin1"]}
            pcbX="0mm"
            pcbY="0mm"
            layer="top"
            shape="rect"
            width="1mm"
            height="0.7mm"
          />
          {antennaSegments.map((segment, index) => (
            <smtpad
              key={index}
              portHints={["pin1"]}
              pcbX={`${segment.pcbX}mm`}
              pcbY={`${segment.pcbY}mm`}
              layer="top"
              shape="rect"
              width={`${segment.width}mm`}
              height={`${segment.height}mm`}
            />
          ))}
          <smtpad
            portHints={["pin1"]}
            pcbX="9mm"
            pcbY="13mm"
            layer="top"
            shape="rect"
            width="0.01mm"
            height="0.01mm"
          />
        </footprint>
      }
    />
  </board>
)
```

## Abse — 2026-06-18T11:23:33.402000+00:00

[attachment]
Attachment: image.png — https://community.tscircuit.com/media/1517127627352309800

## Abse — 2026-06-18T11:23:49.418000+00:00

I managed to make the antenna like this, but this is a hack no ?

## Abse — 2026-06-18T11:24:43.401000+00:00

not sure if we have manual trace component or prop that I'm not aware of ?

## Abse — 2026-06-18T14:33:48.051000+00:00

the trace need from to and from the image he sent the antenna don't have to
Attachment: image.png — https://community.tscircuit.com/media/1517175504023584868

## Abse — 2026-06-19T09:28:05.872000+00:00

https://github.com/tscircuit/system-diagram-proposal/pull/3

## Abse — 2026-06-19T09:28:13.590000+00:00

<@757706909351411845>

## Seve — 2026-06-19T18:43:09.824000+00:00

Did we get in ant of the antenna stuff? Your code there is a crazy hack just use pcbPath of trace

## Seve — 2026-06-19T18:44:04.287000+00:00

The antennaPoints var is nice but the antenna doesnt look right to me- make sure its accurate

## Abse — 2026-06-21T11:23:58.887000+00:00

https://github.com/tscircuit/system-diagram-proposal/pull/4

## Abse — 2026-06-21T11:24:36.766000+00:00

<@757706909351411845> can you review this